As is known, flash-EPROM memories are becoming increasingly important on account of being programmable and erasable electrically. At present, the cells are written by channel hot electron injection, and are erased by Fowler-Nordheim tunneling. In particular, erasing is carried out by applying a high voltage to the source terminal of the cells, with the drain terminal floating and the gate terminal grounded, or by applying a high negative voltage to the gate terminal, with the source terminal grounded or at a medium-high positive voltage, and the drain terminal floating.
At present, flash memories are divided into sectors, with the source terminals of all the cells in the same sector connected to the same source line, so that all the cells in the same sector are erased simultaneously, and the number and size of the sectors (number of bits in each sector) are fixed and unchangeable.
To give a better idea of the problems with the prior art, FIGS. 1 and 2 show the typical architecture of a known flash-EPROM memory device 1.
As shown in FIGS. 1 and 2, known nonvolatile memory device 1 comprises a memory array 2 formed of a number of memory cells 3 arranged in rows and columns and grouped into sectors 4. Each memory cell 3 presents a drain terminal 10 connected to a respective bit line 11, a gate terminal 12 connected to a respective word line 13, and a source terminal 14 connected to a common source line 15. Cells 3 in the same column are connected to the same bit line 11. Cells 3 in the same row are connected to the same word line 13, and cells 3 in the same sector are connected to the same common source line 15, so that each sector 4 presents a respective common source line. In the example shown, the sectors are organized in columns, i.e., the cells in the same column belong to the same sector, but the observations made herein also apply equally to sectors organized in rows.
Word lines 13 (shown schematically in FIG. 1 by arrow 18) are connected to a row decoder 19, which is supplied by a control unit 20 with the coded addresses of the rows to be biased, which addresses are supplied externally or generated inside unit 20 depending on the operation.
Similarly, all the bit lines 11 (shown schematically in FIG. 1 by arrow 22) are connected to a column decoder 21 addressed by control unit 20 so as to appropriately bias and connect bit lines 11 to output lines 23. Output lines 23 are connected to a sense amplify unit 24 also controlled by control unit 20, and which provides for reading the coded information in cells 3 addressed by the bit and word lines, and for supplying this information externally over an output bus 27.
Common source lines 15 are connected to respective switches 25 for grounding or connecting common source lines 15 to a high erase voltage. Switches 25 are controlled by an enabling sector 26, which is in turn controlled by control unit 20.
To erase a sector 4, enabling selector 26, controlled by control unit 20, enables the switch 25 connected to the sector 4 to be erased, so as to bias the source terminals 14 of all the cells at a high voltage (e.g., 12 V). At the same time, gate terminals 12 are grounded or brought to a negative voltage by word lines 13, and drain terminals 10 are left floating, so that all the cells in the sector are erased simultaneously.
As already stated, one drawback of a structure of this type is that the number of cells 3 in sectors 4 and the number of sectors 4 are determined at the design stage with no possibility of being altered, so that, for each customer requirement in terms of number and size of the sectors, memory device 1 must be specially designed, and can only be used for a limited number of applications involving similar requirements.